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Corwin Perren
b300c76103
These are all design documents that I thought I had lost. It's may make me cringe, but it's still cool to use it to see how far I've come.
50 lines
1.5 KiB
Plaintext
50 lines
1.5 KiB
Plaintext
Protel Design System Design Rule Check
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PCB File : C:\Users\Corwin\Google Drive\_Work Related\SARL ECE\PCB Design\PickAndPlace\Final Boards\Light And Switch Panelized\LightSwitchBoard.PcbDoc
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Date : 9/24/2014
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Time : 11:30:23 AM
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Processing Rule : Rule
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Rule Violations :0
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Processing Rule : Net Antennae (Tolerance=0mm) (All)
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Rule Violations :0
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Processing Rule : Silk primitive without silk layer
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Rule Violations :0
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Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
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Rule Violations :0
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Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
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Rule Violations :0
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Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
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Rule Violations :0
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Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)
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Rule Violations :0
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Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
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Rule Violations :0
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Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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Rule Violations :0
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Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Violations Detected : 0
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Time Elapsed : 00:00:00 |