mirror of
https://github.com/caperren/school_archives.git
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Corwin Perren
b300c76103
These are all design documents that I thought I had lost. It's may make me cringe, but it's still cool to use it to see how far I've come.
3 lines
10 KiB
XML
3 lines
10 KiB
XML
<?xml version="1.0"?>
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<PCBDesignProperties2.6><Layers><Board><BoardOnOff>1</BoardOnOff><BoardState>6</BoardState><BoardSpecificOnOff>1</BoardSpecificOnOff><BoardSpecificState>14</BoardSpecificState><BoardSpecificTransState>1</BoardSpecificTransState><ContourOnOff>1</ContourOnOff><ContourState>14</ContourState><ContourTransState>1</ContourTransState><MountingHolesOnOff>1</MountingHolesOnOff><MountingHolesState>14</MountingHolesState><MountingHolesTransState>1</MountingHolesTransState><ObstructAllVisibility>1</ObstructAllVisibility><ObstructAllState>13</ObstructAllState><ObstructViaVisibility>1</ObstructViaVisibility><ObstructViaState>13</ObstructViaState><ObstructTraceVisibility>1</ObstructTraceVisibility><ObstructTraceState>13</ObstructTraceState><ObstructTraceViaVisibility>1</ObstructTraceViaVisibility><ObstructTraceViaState>13</ObstructTraceViaState><OtherHolesOnOff>0</OtherHolesOnOff><OtherHolesState>13</OtherHolesState><OtherHolesTransState>2</OtherHolesTransState><CavityVisibility>1</CavityVisibility><CavityState>12</CavityState><RouteBorderVisibility>1</RouteBorderVisibility><RouteBorderState>13</RouteBorderState></Board><AllLayers><AllTracesAndPadsOnOff>0</AllTracesAndPadsOnOff><AllTracesAndPadsState>1</AllTracesAndPadsState><AllTracesOnOff>1</AllTracesOnOff><AllTracesState>4</AllTracesState><AllTracesTransState>2</AllTracesTransState><AllPadsOnOff>1</AllPadsOnOff><AllPadsState>4</AllPadsState><AllPadsTransState>2</AllPadsTransState><AllPlanesOnOff>1</AllPlanesOnOff><AllPlanesState>12</AllPlanesState><AllPlanesTransState>2</AllPlanesTransState></AllLayers><Layer1><Start>1</Start><EntireLayerOnOff>1</EntireLayerOnOff><EntireLayerState>4</EntireLayerState><TracesOnOff>1</TracesOnOff><TracesState>4</TracesState><TracesTransState>2</TracesTransState><PadsOnOff>1</PadsOnOff><PadsState>4</PadsState><PadsTransState>2</PadsTransState><PlanesOnOff>1</PlanesOnOff><PlanesState>12</PlanesState><PlanesTransState>2</PlanesTransState><End>0</End></Layer1><Layer2><Start>1</Start><EntireLayerOnOff>1</EntireLayerOnOff><EntireLayerState>4</EntireLayerState><TracesOnOff>1</TracesOnOff><TracesState>4</TracesState><TracesTransState>2</TracesTransState><PadsOnOff>1</PadsOnOff><PadsState>4</PadsState><PadsTransState>2</PadsTransState><PlanesOnOff>1</PlanesOnOff><PlanesState>12</PlanesState><PlanesTransState>2</PlanesTransState><End>0</End></Layer2></Layers><Parts><TopParts><TopAllState>10</TopAllState><TopPlacementState>2</TopPlacementState><TopPlacementTransState>2</TopPlacementTransState></TopParts><BottomParts><BottomAllState>12</BottomAllState><BottomPlacementState>2</BottomPlacementState><BottomPlacementTransState>2</BottomPlacementTransState></BottomParts><TopPlacementObstructs><TopPlacementObsState>6</TopPlacementObsState><TopPlacementObsTransState>0</TopPlacementObsTransState></TopPlacementObstructs><BottomPlacementObstructs><BotPlacementObsState>6</BotPlacementObsState><BotPlacementObsTransState>0</BotPlacementObsTransState></BottomPlacementObstructs><TopBondWires><TopBondWires_State>5</TopBondWires_State><TopBondWires_Visibility>2</TopBondWires_Visibility><TopBondWires_State_BoardLevel>5</TopBondWires_State_BoardLevel><TopBondWires_Visibility_BoardLevel>2</TopBondWires_Visibility_BoardLevel><TopBondWires_State_StackLevel_1>5</TopBondWires_State_StackLevel_1><TopBondWires_Visibility_StackLevel_1>2</TopBondWires_Visibility_StackLevel_1><TopBondWires_State_StackLevel_2>5</TopBondWires_State_StackLevel_2><TopBondWires_Visibility_StackLevel_2>2</TopBondWires_Visibility_StackLevel_2><TopBondWires_State_StackLevel_3>5</TopBondWires_State_StackLevel_3><TopBondWires_Visibility_StackLevel_3>2</TopBondWires_Visibility_StackLevel_3><TopBondWires_State_StackLevel_4>5</TopBondWires_State_StackLevel_4><TopBondWires_Visibility_StackLevel_4>2</TopBondWires_Visibility_StackLevel_4></TopBondWires><BottomBondWires><BottomBondWires_State>5</BottomBondWires_State><BottomBondWires_Visibility>2</BottomBondWires_Visibility><BottomBondWires_State_BoardLevel>5</BottomBondWires_State_BoardLevel><BottomBondWires_Visibility_BoardLevel>2</BottomBondWires_Visibility_BoardLevel><BottomBondWires_State_StackLevel_1>5</BottomBondWires_State_StackLevel_1><BottomBondWires_Visibility_StackLevel_1>2</BottomBondWires_Visibility_StackLevel_1><BottomBondWires_State_StackLevel_2>5</BottomBondWires_State_StackLevel_2><BottomBondWires_Visibility_StackLevel_2>2</BottomBondWires_Visibility_StackLevel_2><BottomBondWires_State_StackLevel_3>5</BottomBondWires_State_StackLevel_3><BottomBondWires_Visibility_StackLevel_3>2</BottomBondWires_Visibility_StackLevel_3><BottomBondWires_State_StackLevel_4>5</BottomBondWires_State_StackLevel_4><BottomBondWires_Visibility_StackLevel_4>2</BottomBondWires_Visibility_StackLevel_4></BottomBondWires><TopDiePins><TopDiePins_State>5</TopDiePins_State><TopDiePins_Visibility>2</TopDiePins_Visibility><TopDiePins_State_BoardLevel>5</TopDiePins_State_BoardLevel><TopDiePins_Visibility_BoardLevel>2</TopDiePins_Visibility_BoardLevel><TopDiePins_State_StackLevel_1>5</TopDiePins_State_StackLevel_1><TopDiePins_Visibility_StackLevel_1>2</TopDiePins_Visibility_StackLevel_1><TopDiePins_State_StackLevel_2>5</TopDiePins_State_StackLevel_2><TopDiePins_Visibility_StackLevel_2>2</TopDiePins_Visibility_StackLevel_2><TopDiePins_State_StackLevel_3>5</TopDiePins_State_StackLevel_3><TopDiePins_Visibility_StackLevel_3>2</TopDiePins_Visibility_StackLevel_3><TopDiePins_State_StackLevel_4>5</TopDiePins_State_StackLevel_4><TopDiePins_Visibility_StackLevel_4>2</TopDiePins_Visibility_StackLevel_4></TopDiePins><BottomDiePins><BottomDiePins_State>5</BottomDiePins_State><BottomDiePins_Visibility>2</BottomDiePins_Visibility><BottomDiePins_State_BoardLevel>5</BottomDiePins_State_BoardLevel><BottomDiePins_Visibility_BoardLevel>2</BottomDiePins_Visibility_BoardLevel><BottomDiePins_State_StackLevel_1>5</BottomDiePins_State_StackLevel_1><BottomDiePins_Visibility_StackLevel_1>2</BottomDiePins_Visibility_StackLevel_1><BottomDiePins_State_StackLevel_2>5</BottomDiePins_State_StackLevel_2><BottomDiePins_Visibility_StackLevel_2>2</BottomDiePins_Visibility_StackLevel_2><BottomDiePins_State_StackLevel_3>5</BottomDiePins_State_StackLevel_3><BottomDiePins_Visibility_StackLevel_3>2</BottomDiePins_Visibility_StackLevel_3><BottomDiePins_State_StackLevel_4>5</BottomDiePins_State_StackLevel_4><BottomDiePins_Visibility_StackLevel_4>2</BottomDiePins_Visibility_StackLevel_4></BottomDiePins><Eps><AllEpsToggle>1</AllEpsToggle><AllEpsState>14</AllEpsState><AllResistiveToggle>1</AllResistiveToggle><AllResistiveState>14</AllResistiveState><AllCapacitiveEpsToggle>1</AllCapacitiveEpsToggle><AllCapacitiveEpsState>14</AllCapacitiveEpsState><AllConductiveEpsToggle>1</AllConductiveEpsToggle><AllConductiveEpsState>14</AllConductiveEpsState></Eps></Parts><AuxilaryGraphicsAndPCBs><AllAuxilaryGraphicsAndPCBsToggle>1</AllAuxilaryGraphicsAndPCBsToggle><AllAuxilaryGraphicsAndPCBsState>5</AllAuxilaryGraphicsAndPCBsState><AuxilaryGraphicsToggle>1</AuxilaryGraphicsToggle><AuxilaryGraphicsState>8</AuxilaryGraphicsState><AuxilaryPCBsToggle>1</AuxilaryPCBsToggle><AuxilaryPCBsState>12</AuxilaryPCBsState></AuxilaryGraphicsAndPCBs><TabExpand><LayerTabExpand><LayerTabExpand>1</LayerTabExpand><LayerTabExpand>1</LayerTabExpand><LayerTabExpand>1</LayerTabExpand><LayerTabExpand>1</LayerTabExpand></LayerTabExpand><PartTabExpand><PartTabExpand>1</PartTabExpand><PartTabExpand>1</PartTabExpand><PartTabExpand>1</PartTabExpand></PartTabExpand><AssemblyTabExpand><AssemblyTabExpand>1</AssemblyTabExpand><AssemblyTabExpand>1</AssemblyTabExpand><AssemblyTabExpand>1</AssemblyTabExpand></AssemblyTabExpand></TabExpand><RefDes><AllRefDesToggle>1</AllRefDesToggle><AllRefDesSelect>0</AllRefDesSelect><AllRefDesState>2</AllRefDesState><Start>1</Start><RefDesName>D1</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>1</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D2</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>2</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D3</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>3</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D4</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>4</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D5</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>5</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D6</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>6</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D7</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>7</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D8</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>8</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D9</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>9</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D10</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>10</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D11</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>11</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D12</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>12</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D13</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>13</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>D14</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>14</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>J1</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>15</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>J2</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>16</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>J3</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>17</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>J4</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>18</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>R1</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>19</UID><RefDesState>2</RefDesState><End>0</End><Start>1</Start><RefDesName>R2</RefDesName><ToggleRefDes>1</ToggleRefDes><UID>20</UID><RefDesState>2</RefDesState><End>0</End></RefDes><Thick><ToggleThickTrace>0</ToggleThickTrace><ToggleThickPad>1</ToggleThickPad></Thick><RenderMode><SelectRenderMode>2</SelectRenderMode></RenderMode></PCBDesignProperties2.6>
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