Altium

Design Rule Verification Report

Date	:	9/22/2014
Time	:	2:44:44 PM
Elapsed Time	:	00:00:00
Filename	:	C:\Users\Corwin\Google Drive\_Work Related\SARL ECE\PCB Design\PickAndPlace\Final Boards\Switch Board\Switch Board.PcbDoc

Warnings	:	0
Rule Violations	:	8

Summary

Warnings	Count
Total	0

Rule Violations	Count
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Clearance Constraint (Gap=0.254mm) (All),(All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)	0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)	0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)	8
Silk to Silk (Clearance=0.254mm) (All),(All)	0
Silk primitive without silk layer	0
Net Antennae (Tolerance=0mm) (All)	0
Rule	0
Total	8

Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Track (61.722mm,84.709mm)(61.722mm,88.265mm) Top Overlay	Pad J1-1(62.992mm,86.487mm) Top Layer
Track (64.262mm,84.709mm)(64.262mm,88.265mm) Top Overlay	Pad J1-1(62.992mm,86.487mm) Top Layer
Track (61.722mm,84.709mm)(64.262mm,84.709mm) Top Overlay	Pad J1-1(62.992mm,86.487mm) Top Layer
Track (61.722mm,88.265mm)(64.262mm,88.265mm) Top Overlay	Pad J1-1(62.992mm,86.487mm) Top Layer
Track (71.628mm,84.709mm)(71.628mm,88.265mm) Top Overlay	Pad J2-1(72.898mm,86.487mm) Top Layer
Track (74.168mm,84.709mm)(74.168mm,88.265mm) Top Overlay	Pad J2-1(72.898mm,86.487mm) Top Layer
Track (71.628mm,84.709mm)(74.168mm,84.709mm) Top Overlay	Pad J2-1(72.898mm,86.487mm) Top Layer
Track (71.628mm,88.265mm)(74.168mm,88.265mm) Top Overlay	Pad J2-1(72.898mm,86.487mm) Top Layer